Laboratory for Internet and Innovative Technologies

Memory access is the bottleneck of all computations. CPU cache is introduced to speed up accessing reused and local data. Matrix multiplication is the most common representative of many linear algebra algorithms which performance directly depends of the cache. Many cache parameters exist and impact the overall computing performance such as cache type, line, size, level, associativity, and replacement policy. Therefore an optimal architecture to execute certain compute and memory intensive algorithm is desirable in most applications. We have developed MMCacheSim simulator to predict matrix multiplication performance on particular existing or non-existing multiprocessor. MMCacheSim simulates the execution time and number of cache misses that matrix multiplication algorithm performs with particular matrix size and element size executing on processor with diļ¬€erent cache size, line, level associativity, and replacement policy.


Blagoj Atanasovski, Sasko Ristov, Marjan Gusev, and Nenad Anchev


CPU Cache, Multiprocessor, HPC, Simulation

Full Paper

The technical report is published as a paper in ICT Innovations 2012, (Editors Gusev and Markovski) web proceedings, ISSN 1857-7288, 2012